The present invention relates generally to error detection logic for computer systems and more particularly to an error detection and capture mechanism for detecting and capturing errors which occur over a peripheral bus in a multiple bus computer system.
Computer systems typically include more than one bus, each bus in the system having devices attached thereto which communicate locally with each other over the bus. Examples of the different types of buses present in typical computer systems are a system bus to which a host central processing unit is attached and one or more peripheral buses. System-wide communication over different buses is required, however, if a device attached to one bus needs to read or write information to or from a device on another bus. To permit system-wide communication between devices on different buses, bus-to-bus bridges (interfaces) are provided to match the communications protocol of one bus with that of another.
Known bus-to-bus bridges include those disclosed in the following co-pending patent applications assigned to the IBM Corporation: application Ser. No. 08/815,992 entitled "BUS CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE"; U.S. Pat. No. 5,313,627 issued May 17, 1994 entitled "PARITY ERROR DETECTION AND RECOVERY"; application Ser. No. 07/816,204 entitled "CACHE SNOOPING AND DATA INVALIDATION TECHNIQUE"; U.S. Pat. No. 5,255,374 issued Oct. 19, 1993 entitled "BUS INTERFACE LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE"; application Ser. No. 07/816,691 entitled "BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT"; U.S. Pat. No. 5,265,211 issued Nov. 23, 1993 entitled "BUS INTERFACE FOR CONTROLLING SPEED OF BUS OPERATION"; application Ser. No. 07/816,116 entitled "ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE"; and application Ser. No. 07/816,698 entitled "METHOD AND APPARATUS FOR DETERMINING ADDRESS LOCATION AT BUS TO BUS INTERFACE", all filed on Jan. 2, 1992. These applications describe mechanisms which permit system-wide communication of devices attached to different buses in the system.
Each bus-to-bus bridge in a multi-bus computer system is used to connect two buses in the system. Various types of buses are available to construct a given computer system. One such bus which is becoming widely accepted is the PCI (Peripheral Component Interconnect) bus, which is capable of performing significant data transfer in a relatively short period of time (up to 120 megabytes of data per second). The PCI bus achieves this high level of performance, in part, because it may be directly linked to other high speed buses, such as system buses to which a CPU may be connected, and thus may provide for rapid transfer of data between devices attached to the PCI bus and devices attached to the system bus. In fact, the operation of several high integration devices, such as certain graphics package controllers, require a direct link to a system bus through a high performance bus such as the PCI bus. In addition, the PCI bus architecture does not require any "glue logic" to operate peripheral devices connected to it. Glue logic for other buses typically consists of miscellaneous hardware components such as decoders, buffers or latches that are installed intermediate the peripheral devices and the bus.
The primary PCI bus operates on a synchronous clock signal of 33 MHz, and the strings of data transmitted over the PCI bus are 32 bits long. A 32-bit data string on the PCI bus is called a double word (DWORD), which is divided into 4 bytes each comprised of 8 bits of data. The address and data information carried by the PCI bus are multiplexed onto one signal. Multiplexing eliminates the need for separate address and data lines, which in turn, reduces the amount of signals required in a PCI bus environment as opposed to other bus architectures. The number of signals required in PCI bus architecture is between 45-47 while non-multiplexed buses typically require twice this number. Accordingly, because the number of signals are reduced, the number of connection pins required to support a device linked to the PCI bus is also reduced by a corresponding number. PCI architecture is thus particularly adapted for highly integrated desktop computer systems.
A more detailed description of the structure and operation of PCI bus architecture is provided in "Peripheral Component Interconnect (PCI) Revision 2.0 Specification", published Apr. 30, 1993; "Preliminary PCI System Design Guide", revision 0.6 published Nov. 1, 1992, and "Peripheral Component Interconnect (PCI) Add-in Board/Connector Addendum", (Draft) published 6 Nov. 1992; all by the PCI Special Interest Group, the contents of which references are incorporated herein by reference as if they were fully set forth.
Interfacing the PCI bus to other buses such as a host system bus in a computer system is problematic, however, if the communications protocols between the PCI bus and the host system bus are different. For example, although the PCI bus specification provides for PCI bus communications parity errors to be detected and reported over the PCI bus, no means exist for either recovering from these errors or for reporting these errors over the host system bus for management by the CPU.
It is an object of the present invention, then, to provide a mechanism for detecting and capturing errors which occur over a peripheral bus, such as a PCI bus, in a multiple bus computer system. It is a further object of the invention to provide a mechanism whereby such errors are reported over a host system bus, which is interfaced with the peripheral bus, for use in handling and recovering from the error conditions.